A conventional CMOS device is illustrated in FIG. 1. The CMOS device 10 comprises a silicon substrate 12 which illustratively is N-type. The dopant concentration of the N-type substrate is 2.times.10.sup.15 /cm.sup.3. A P-well 14 is formed on the surface of the substrate 12 by diffusion for example. The depth of the P-well 14 is 1.8 .mu.m and the dopant concentration of the P-well is 8.times.10.sup.16 /cm.sup.3. An N-well 16 is also formed on the surface of the substrate 12. The N-well 16 has a depth of 2 .mu.m and a dopant concentration of 6.times.10.sup.16 /cm.sup.3.
The CMOS device 10 comprises a P-MOS device 20 formed in the N-well 16 and an N-MOS device 30 formed in the P-well 14. The P-MOS device 20 comprises a source region 24 and a drain region 22 separated by a channel 26. The gate 28 which is connected to the input voltage V.sub.in controls the conductivity of the channel 26. The source 24 is connected to the positive supply voltage V.sub.DD. The source and drain regions 24 and 22 are doped P.sup.+ type with a dopant concentration of 10.sup.20 /cm.sup.3 and a depth of 0.25 .mu.m. The positive supply voltage V.sub.DD is also connected to the N.sup.+ type surface contact region 29 which may be used in addition to the gate 28 for controlling the channel 26. The N.sup.+ contact 29 has a depth of 0.2 .mu.m and a dopant concentration of 10.sup.20 /cm.sup.3.
The N-MOS device 30 formed in the P-well 14 has a source region 34 and a drain region 32 separated by a channel 36. The gate 38 which is connected to V.sub.in in controls the conductivity of the channel 36. The source 34 is connected to the negative supply voltage V.sub.ss. The source and drain regions 34 and 32 are doped P.sup.+ type with a concentration of 10.sup.20 /cm.sup.3 and a depth of 0.25 .mu.m. The negative supply voltage V.sub.ss is also connected to the P.sup.+ type surface contact region 39. The contact region 39 can be used in addition to the gate 38 for controlling the channel 36. The P.sup.+ region 39 has a depth of 0.25 .mu.m and a dopant concentration of 10.sup.20 /cm.sup.3.
There are two parasitic bipolar junction transistors in the CMOS device 10 of FIG. 1. The parasitic bipolar junction transistors are labeled T.sub.1 and T.sub.2. T.sub.1 is a PNP transistor with a collector resistance R.sub.p. T.sub.2 is an NPN transistor with a collector resistance R.sub.N. T.sub.1 is formed by the P.sup.+ source and drain regions 22 and 24 and the bulk of the P-well 14 and N-well 16. T.sub.2 is formed by the N.sup.+ source and drain regions 32 and 34 and the bulk of the N-well 16 and P-well 14. The two parasitic transistors T.sub.1 and T.sub.2 form a parasitic thyristor. This thyristor normally has no effect as T.sub.1 and T.sub.2 are in the off state. However, under some circumstances the thyristor T.sub.1 and T.sub.2 may fire. In this case, the parasitic transistors T.sub.1 and T.sub.2 are turned on, thereby short circuiting the positive supply voltage V.sub.DD to the negative supply voltage V.sub.ss. The resulting high currents will destroy the CMOS device 10. This effect is called the "latch-up" effect. The "latch-up" effect is described in detail in U. TETZE & C. SCHENK, ELECTRONIC CIRCUITS: DESIGN AND APPLICATIONS, pp. 193-194 (1991).
A variety of techniques have been proposed in the prior art to provide immunity with respect to latch-up. These techniques generally involve reducing the current gains of the transistors T.sub.1 and T.sub.2 and the resistances R.sub.p and R.sub.N. The prior art techniques include, for example, heavy doped substrate EPI wafer, retrograde well-etc.
These techniques generally involve lengthening the distance between the P.sup.+ region 22 and the N.sup.+ region 32, thus inevitably reducing the packing density of CMOS devices in an integrated circuit. To achieve a balance between packing density and latch-up immunity, a P.sup.+ type guard ring 52 is formed in the P-well 14 and N.sup.+ type guard ring 62 is formed in the N-well 16. The purpose of the guard ring 62 is to collect the current flowing to the base of T.sub.1 and the purpose of the guard ring 52 is to collect the current flowing to the base of T.sub.2. The current collected by the guard ring 62 is designated i.sub.1 ' and the current collected by the guard ring 52 is designated i.sub.2 '.
As the fabrication process of a CMOS integrated circuit improves, the size of the device 10 scales down and the distance between N.sup.+ region 32 and P.sup.+ region 22 decreases. In addition, the depth of the P-well 14 and N-well 16 becomes shallow. Consequently, the value of the current gains of T.sub.1 and T.sub.2 increase as do the resistances R.sub.p and R.sub.N. This makes it easier for latch-up to occur. In particular, the depth of the guard ring is generally equal to the depth of the source and drain regions. This limits the ability of the guard rings to collect the base currents of the parasitic bipolar junction transistors. To overcome this disadvantage, the width of the guard rings is usually increased at the expense of circuit packing density.
In view of the foregoing, it is an object of the present invention to provide a CMOS device which overcomes the above-described disadvantages of the prior art. In particular, it is an object of the invention to provide a CMOS device having a guard ring which provides immunity against latch-up and which also does not substantially reduce circuit packing density.